
Professor of Electrical and Computer Engineering
David Atienza Alonso is a professor of Electrical and Computer Engineering, Head of the Embedded Systems Laboratory (ESL) and Scientific Director of the EcoCloud Sustainable Computing Center at EPFL, Switzerland. He received his MSc and Ph.D. degrees in computer science and engineering from UCM, Spain, and IMEC, Belgium, in 2001 and 2005, respectively. His research interests include system-level design methodologies for high-performance multi-processor system-on-chip (MPSoC) and low-power Internet-of-Things (IoT) systems, including new 2-D/3-D thermal-aware design for MPSoCs and many-core servers, ultra-low power edge AI architectures for wireless body sensor nodes and smart embedded systems, HW/SW reconfigurable systems, dynamic memory optimizations, and network-on-chip design.
Dr. Atienza has co-authored more than 400 papers, three books, and 14 licensed patents in these previous areas. He has also received several recognitions and awards, among them, the ICCAD 10-Year Retrospective Most Influential Paper Award in 2020, Design Automation Conference (DAC) Under-40 Innovators Award in 2018, the IEEE TCCPS Mid-Career Award in 2018, an ERC Consolidator Grant in 2016, the IEEE CEDA Early Career Award in 2013, the ACM SIGDA Outstanding New Faculty Award in 2012, and a Faculty Award from Sun Labs at Oracle in 2011. He has also earned several best paper awards at top conferences in the areas of electronic design automation (EDA), embedded and cyber-physical systems, and medical devices. He serves or has served as Editor-in-Chief of IEEE Trans. on CAD (T-CAD), and as associate editor of IEEE Trans. on Computers (TC), IEEE Transactions on Emerging Topics in Computing (TETC), ACM Computing Surveys (CSUR), IEEE Design & Test of Computers (D&T), IEEE T-CAD, IEEE Transactions on Sustainable Computing (T-SUSC), ACM Journal on Emerging Technologies in Computing Systems (JETC), ACM Transactions on Embedded Computing Systems (TECS), and Elsevier Integration. He was the Technical Program Chair of DATE 2015 and General Chair of DATE 2017. He served as President of IEEE CEDA in the period 2018-2019, and is currently the Chair of the European Design Automation Association (EDAA). He is a Fellow of IEEE and of ACM.
Contact Information
- Email Address: david.atienza@epfl.ch
- Websites:
Research Interests
System-level design methodologies for high-performance multi-processor system-on-chip (MPSoC) and low-power Internet-of-Things (IoT) systems, including new 2-D/3-D thermal-aware design for MPSoCs and many-core servers, ultra-low power edge AI architectures for wireless body sensor nodes and smart embedded systems, HW/SW reconfigurable systems, dynamic memory optimizations, and network-on-chip design.